View MSM7718-01_240692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2U0052-18-86
Semiconductor MSM7718-01
Semiconductor Echo Canceler with ADPCM CODEC
This version: Aug. 1998 MSM7718-01
GENERAL DESCRIPTION
The MSM7718, developed for PHS (Personal Handyphone System) applications, is a CMOS LSI device and contains a line echo canceler and a single channel full-duplex ADPCM transcoder that performs interconversion between voice-band analog signal and 32 kbps ADPCM data. This device includes DTMF tone and several types of tone generation, transmit/receive data mute and gain control, and VOX function and is best suited for master telephones in PHS applications.
FEATURES
* Single 3 V power supply VDD : 2.7 V to 3.6 V * ADPCM : ITU-T Recommendations G.726 (32 kbps) * Full-Duplex single channel operation * Transmit/receive synchronous mode * PCM interface coding format : -law * Built-in line echo canceler Echo attenuation : 30 dB (typ.) Cancelable echo delay time : Normal speech mode : 23 ms (max.) Line echo canceler expansion mode : 54 ms (max.) * Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps * Low power consumption Operating mode : Typically 66 mW (VDD = 3.0 V) Power-down mode : Typically 0.3 mW (VDD = 3.0 V) * Two analog input gain adjustable amplifier stages * Analog output stage : Push-pull drive, (direct drive of 350 W + 120 nF) * Master clock frequency : 9.600/19.200 MHz * Transmit/receive mute, transmit/receive programmable gain control * Built-in DTMF tone generator and various ringing tones generator * DTMF tone and call progress tone detection * Serial MCU interface control * Built-in VOX control Transmit side : Voice/silence detect Receive side : Background noise generation at the absence of voice signal * Built-in 2100 Hz tone detection (bidirectional) * Package: 100-pin plastic TQFP (TQFP100-1414-0.50-K) (Product name : MSM7718-01TS-K)
1/38
Semiconductor
MSM7718-01
BLOCK DIAGRAM
ATTtgrx
Tone Generator (DTMF etc.) Tone Detector (DTMF etc.)
ATTtgtx
ATTtx + - SinL
ATTsL
Center Clip SoutL
Line Adapive FIR Filter (LAFF) Coeff.L0 Coeff.L1
Power Calc. Howling Detector Double Talk Detector
RoutL
RinL
ATTrx
GainL ATTrL Line Echo Canceler
L/m m/L
2100 Hz Detect
m/L L/m Mute
Power Detect
Noise Gen.
VOXO
Voice Detect
VOXI
PCM CODEC SGR SGT AIN1- AIN1+ GSX1 AIN2 GSX2 VFRO PWI AOUT- AOUT+
- + - +
VREF L/m BPF ADC RC LPF RC LPF 1.2 kW
- +
Flash Memory Controller (Reserved) ADPCM TRANSCODER
MLV0 MLV1 MLV2 MUTE D7-0 A20-0 WE OE CS1 CS2 RP IS BCLKA SYNCA IR
DAC LPF
ADPCM CODER ADPCM DECODER
P/S&S/P Timing Gen. Clock Gen.
P/S
-1 1.2 kW m/L
S/P
MCU Interface
Test Interface
MCKSL MCK PDN/RST PDWN
PCMPCI PCMPCO PCMLNI PCMLNO PCMACI PCMACO PCMADI PCMADO
VDDD1,2,3 VDDA DG1,2,3 AG DEN EXCK DIN DOUT INT
SYNCP BCLKP
TSTI1-4
TSTO
2/38
Semiconductor
MSM7718-01
99 PCMADO
98 PCMACO
95 PCMPCO
96 PCMLNO
92 PCMADI
91 PCMACI
89 PCMPCI
90 PCMLNI
85 SYNCA
87 BCLKP
84 BCLKA
81 PDWN
83 TSTI1
93 DOUT
82 VDDD3
97 DG3
77 CS1
79 WE
88 NC
80 RP
100 NC
NC TSTI2 PDN/RST DIN EXCK DEN VDDD1 SYNCP TSTI4
1 2 3 4 5 6 7 8 9
76 NC
75 NC 74 CS2 73 INT 72 TSTO 71 VOXO 70 VOXI 69 MLV0 68 MLV1 67 MLV2 66 MUTE 65 DG2 64 D7 63 NC 62 D6 61 D5 60 D4 59 D3 58 D2 57 D1 56 D0 55 A0 54 A1 53 A2 52 VDDD2 51 NC
TSTI3 10 MCK 11 MCKSL 12 GNDA 13 VFRO 14 PWI 15 AOUT- 16 AOUT+ 17 SGT 18 SGR 19 NC 20 NC 21 AIN1- 22 GSX1 23 AIN1+ 24 NC 25
AIN2 28
VDDA 29
DG1 30
A20 31
A19 32
A18 33
A17 34
A16 35
A15 36
NC 37
A14 38
A13 39
A12 40
A11 41
A10 42
A9 43
A8 44
A7 45
A6 46
A5 47
A4 48
78 OE
86 IR
94 IS
A3 49
GSX2 27
NC: No-connect pin 100-Pin Plastic TQFP
NC 50
NC
26
3/38
Semiconductor
MSM7718-01
PIN FUNCTIONAL DESCRIPTION
AIN1+, AIN1-, AIN2, GSX1, GSX2 Transmit analog inputs and the outputs for transmit gain adjustment. AIN1- (AIN2) connects to inverting input of the internal transmit amplifier. AIN1+ connects to noninverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the internal transmit amplifier output. Refer to Fig.1 for gain adjustment. VFRO, AOUT+, AOUT-, PWI Receive analog outputs and the output for receive gain adjustment. VFRO is the receive filter output. AOUT+ and AOUT- are differential analog signal outputs which can directly drive ZL (= 350 W + 120 nF) or a 1.2 kW load. Refer to Fig.1 for gain adjustment. However, these outputs are in high impedance state during power-down.
AIN1- Differential Analog Input V1 C1 R1 R2 AIN1+ C1 R1 R2 GSX1 SGT AIN2 C2 R3 R4 Transmit Gain: V GSX2 /Vi = (R2/R1) (R4/R3) Receive Gain: V O /V VFRO = 2 (R5/R6) GSX2 VFRO
- +
VREF
+ -
- +
to ENCODER
from DECODER R6 PWI R5 AOUT- Differential Analog Output
- +
Z L =120 nF + 350 W
VO
AOUT+
-1
Figure 1 Analog Interface 4/38
Semiconductor SGT, SGR
MSM7718-01
Outputs of the analog signal ground voltage. SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the analog signal ground voltage for the receive system. The output voltage is approximately 1.4 V. Connect bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. However to reduce the response time of the receiver power-on, it is recommended to apply bypass capacitors of 1 mF and 0.1 mF. During power-down, the output changes to 0 V. AG Analog ground. DG1, 2, 3 Digital ground. VDDA +3 V power supply for analog circuits. VDDD1, 2, 3 +3 V power supply for digital circuits. PDN/RST Power-down reset control input. A logic "0" makes the LSI device enter a power-down state. At the same time, all control register data is reset to the initial state. Set this pin to a logic "1" during normal operating mode. Since the PDN/ RST pin is ORed with CR0-B5 of the control register, set CR0-B5 to digital "0" when using this pin. PDWN Power-down control input. When set to a logic "0", the device changes to the power-down state, but each bit of control register and internal variables of control register are retained. During normal operation, set this pin to logic "1". Since the PDWN pin is ORed with CR0-B6 of the control register, set CR0-B6 to logic "0" when using this pin. MCK Master clock input. The frequency must be 9.6 MHz or 19.2 MHz. The master clock signal is allowed to be asynchronous with SYNCP, SYNCA, BCLKP, and BCLKA.
5/38
Semiconductor MCKSL
MSM7718-01
Master clock selection input. Set MCKSL to logic "0" when the master clock frequency is 9.6 MHz, and to logic "1" when it is 19.2 MHz. PCMPCO PCM data output of the PCM CODEC. PCM is output from MSB, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain. PCMPCI PCM data input of the PCM CODEC. PCM is shifted in at the falling edge of the BCLKP signal. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. PCMADO PCM data output of the ADPCM transcoder. PCM is the output data after ADPCM decoder processing and is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR1-B5. (The time slot 1 or 2 can be selected. Refer to Figs. 2-4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in an high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain. PCMADI PCM data input of the ADPCM transcoder. PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR1-B5. (The time slot 1 or 2 can be selected. Refer to Figs. 2-4.) PCMLNO PCM receive data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B3 to B5. (The time slot of 1 to 7 can be selected. Refer to Figs. 2-4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain.
6/38
Semiconductor PCMLNI
MSM7718-01
PCM transmit data input of the line echo canceler. PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM mutiplexing by the control register CR2-B3 to B5. (One of the time slots 1 to 7 can be selected. Refer to Figs. 2-4.) PCMACO PCM transmit data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B0 to B2. (The time slot 1 to 7 can be selected. Refer to Figs. 2 - 4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance sate during power down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain. PCMACI PCM receive data input of the line echo canceler. PCM is shifted in at a falling edge of BCLKP and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B0 to B2. (One of the time slots 1 to 7 can be selected. Refer to Figs. 2-4.)
BCLKP SYNCP PCM Multiple time slot 1 time slot 2 time slot 3 time slot 7
Note : The PCM signals (PCMPCI and PCMPCO) of the PCM CODEC are always assigned to time slot 1. The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to time slot 1 or 2. The PCM signals (PCMLNI, PCMLNO, PCMACI, PCMACO) of the line echo canceler can be assigned to one of the time slots 1 to 7. (Multiple timing is controlled by CR1 and CR2.) Figure 2 PCM Multiple Timing
7/38
Semiconductor
MSM7718-01
MSM7718 Line Echo Canceler
Line
PCM CODEC
PCMPCI PCMPCO PCMLNI PCMACI PCMLNO PCMACO PCMADI PCMADO
ADPCM Transcoder
Slave telephone
Note : In this connection, PCMLNI, PCMLNO, PCMACI, and PCMACO should all be assigned to time slot 1 for their output timing (the output timing for the PCM CODEC is always assigned to time slot 1). Turn on the line echo canceler and establish a route between the slave telephone and the line. Figure 3 PCM Signal Connection Example 1
8/38
Semiconductor
MSM7718-01
MSM7718 Line Echo Canceler
Line
PCM CODEC PCMPCI PCMPCO PCMLNI PCMACI PCMLNO PCMACO PCMADI PCMADO
ADPCM CODEC
Slave telephone
Microphone and speaker of the master telephone
PCM CODEC
Notes : The PCM signals of the ADPCM transcoder are assigned to time slot 2. (The PCM signals of the PCM CODEC are always assigned to time slot 1.) The PCM signals of an external PCM CODEC are assigned to time slot 3. Route between the line and the slave telephone PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are assigned to time slot 2. Turn on the line echo canceler, and establish the route between the line and the slave telephone. Route between the master telephone's microphone/speaker (handsfree) and the slave telephone PCMLNI and PCMLNO are assigned to time slot 3 and PCMACI and PCMACO are assigned to time slot 2. Turn on the line echo canceler, and establish the route between the microphone/ speaker of the master telephone and the slave telephone. Route between the line and the master telephone's microphone/speaker (handsfree) PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are assigned to time slot 3. Put the line echo canceler into "through mode", and establish the route between the line and the microphone/speaker of the master telephone. Various routing can be implemented providing extension of external PCM CODECs. Figure 4 PCM Signal Connection Example 2
9/38
Semiconductor BCLKP
MSM7718-01
Shift clock input for the PCM data (PCMPCO, PCMPCI, PCMADO, PCMADI, PCMLNO, PCMLNI, PCMACO, PCMACI). The frequency is set in the range of 64 kHz to 2048 kHz. This signal must be synchronized with the SYNCP signal. (Refer to Fig. 2.) SYNCP 8 kHz synchronous signal input for transmit and receive PCM data. This signal must be synchronized with the BCLKP signal. (Refer to Fig. 2.) IS Transmit ADPCM data output. This data is the output data after ADPCM encoding, and is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA. This pin is an open drain output which remains in a high impedance state during power-down, and requires a pull-up resistor. IR Receive ADPCM data input. ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input orderly from MSB. BCLKA Shift clock input for the ADPCM data (IS, IR). The frequency is from 64 kHz to 2048 kHz. This signal must be synchronized with the SYNCA signal. SYNCA 8 kHz synchronous signal input for transmit and receive ADPCM data. Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial ADPCM data stream. DEN, EXCK, DIN, DOUT, INT Serial control ports for MCU interface. Reading and writing data is performed by an external MCU through these pins. 17-byte control registers are provided in this device. DEN is the "Enable" control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Input/output timing is shown in Fig. 5. INT goes to logic "0" when any change has been found in the tone detection results in the tone detection mode (change in the control register bits CR7-B3, B2), and goes to logic "1" when the data of control register CR7 is read out.
10/38
Semiconductor
DEN
EXCK DIN
DOUT
DEN
EXCK DIN
DOUT
VOXO
Signal output for transmit VOX function. The VOX function recognizes the presence or absence of the transmit voice signal by detecting the level of the transmit signal to the line echo canceler . "1" and "0" levels set to this pin correspond to the presence and the absence of voice, respectively. This result appears also at the register data CR7-B7. The signal energy detect threshold is set by the control register data CR6-B6, B5. The timiging diagram of the VOX function is shown in Fig 6. The transmit signal to the line echo canceler refers to the signal input to the PCMLNI pin. VOXI
Signal input for receive VOX function. The "1" level at VOXI indicates the presence of a voice signal, the decoder block processes normal receive signal, and the voice signal on the PCMACI pin goes through. The "0" level indicates the absence of a voice signal and the background noise generated in this device is output to the line echo canceler. The background noise amplitude is set by the control register CR6. Because this signal is ORed with the register data CR6-B3, set the control register data CR6-B3 to logic "0".
, ,, ,
MSM7718-01
W A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 High Impedance (a) Data Write Timing R A4 A3 A2 A1 A0 High Impedance B7 B6 B5 B4 B3 B2 B1 B0 (b) Data Read Timing
Figure 5 MCU Interface Input/Output Timing
11/38
Semiconductor
MSM7718-01
Voice Input GSX2 Silence VOXO TVXON Voice Detect Voice Voice TVXOFF Silence Detect (Hangover time)
(a) Transmit VOX Function Timing Diagram (for Analog Input)
Silence VOXI Voice Voice
Voice Output VFRO Normal Voice Signal Decoded Time Period Background Noise
(b) Receive VOX Function (CR6-B3: logic "0") Timing Diagram (for Analog Input)
Note: The VOX function is valid when CR6-B7 is set to logic "1". Figure 6 VOX Function MUTE This pin is used to enable the receive side voice path mute level. To set the mute level, set this pin to "1". MLV0, MLV1, MLV2 These pins are used to set the receive side voice path mute level. For the control method, refer to the control register description (CR1). Since these pins are ORed with CR1-B2, B1, and B0 internally, set the bits of the register to "0" before using this pin.
12/38
Semiconductor D7 to D0 (reserved for external memory I/F) Output of write data, and input-output of read data. A20 to A0 (reserved for external memory I/F) External memory address output. WE (reserved for external memory I/F) Output for write control . OE (reserved for external memory I/F) Output for read control. CS1, CS2 (reserved for external memory I/F) Chip select output. RP (reserved for external memory I/F) Reset/power-down control output for external memory. TSTI1, TSTI2, TSTI3, TSTI4 Input for test. Normally fix these pins to logic "0". TSTI4
MSM7718-01
Input for mode select. Fix this pin to logic "0" for normal speech mode. Fix this pin to logic "1" for line echo canceler expansion mode. Refer to the explanation of CR0 for the operation mode. TSTO Output for test.
13/38
Semiconductor
MSM7718-01
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +5 - 0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Master Clock Frequency Master Clock Duty Ratio Bit Clock Frequency Synchronous Pulse Frequency Clock Duty Cycle Symbol VDD Ta VIH VIL tIr tIf fMCK DC fBCK fSYNC DCK tXS Transmit Sync Pulse Setting Time tSX tXO tRS Receive Sync Pulse Setting Time tSR tRO Receive Sync Pulse Setting Time PCM, ADPCM Setup Time PCM, ADPCM Hold Time tWS tDS tDH Condition -- -- All digital inputs All digital inputs All digital inputs All digital inputs MCK MCK BCLKP, BCLKA SYNCP, SYNCA BCLKP, BCLKA, EXCK BCLKP to SYNCP, BCLKA to SYNCA SYNCP to BCLKP, SYNCA to BCLKA
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Max. Min. Typ. Unit 2.7 -25 0.45 VDD 0 -- -- 40 64 -1000ppm 40 100 100 -- 100 100 -- 1 BCLK 100 100 -- +25 -- -- -- -- 50 -- 8.0 50 -- -- -- -- -- -- -- -- -- 3.6 +70 -- 0.16 VDD 50 50 60 2048 +1000ppm 60 -- -- 100 -- -- 100 100 -- -- V C V V ns ns MHz % kHz kHz % ns ns ns ns ns ns ms ns ns
-100ppm 19.2/9.6 +100ppm
SYNCP to BCLKP, SYNCA to BCLKA
BCLKP to SYNCP, BCLKA to SYNCA SYNCP to BCLKP, SYNCA to BCLKA
SYNCP to BCLKP, SYNCA to BCLKA
SYNCP, SYNCA -- --
Note: If SYNCP and SYNCA are generated from different clocks, do not change the relative timing of the rising edge of SYNCP and that of SYNCA (that is, which rising edge is earlier) after the reset state has been released.
14/38
Semiconductor
MSM7718-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD= 2.7 to 3.6 V, Ta= -25 to +70C) Parameter Power Supply Current 1 Power Supply Current 2 Input Leakage current High Level Digital Output Voltage Low Level Digital Output Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IIH IIL VOH1 VOH2 VOL IO CIN Condition Operating mode, no signal (only the master clock is input) Power down mode (only the master clock is input) VI=VDD VI = 0 V IOH= 0.4 mA IOH= 1 mA
1LSTTL, pull-up resistance : 500 W
Min. -- -- -- -- 0.5VDD 0.8VDD 0 --
Typ. 22 0.2 -- -- -- -- 0.2 -- 5
Max. 40 1 2 0.5 VDD VDD 0.4 10 --
Unit mA mA mA mA V V V mA pF
IS --
--
Analog Interface Characteristics
(VDD= 2.7 to 3.6 V, Ta= -25 to +70C) Parameter Input Resistance Output Load Resistance Symbol RIN RL1 RL2 RL3 CL1 Output Load Capacitance CL2 CL3 VO1 Output Voltage Level (*1) VO2 VO3 Offset Voltage SGT, SGR Output Voltage SGT Output Impedance SGR Output Impedance VOFGX VOFGX VSG RSGT RSGR Condition AIN+, AIN-, AIN2, PWI GSX1, GSX2, VFRO AOUT+ AOUT- GSX1, GSX2, VFRO AOUT+ AOUT- GSX1, GSX2, VFRO (RL=20kW) AOUT+ (RL=1.2 kW) AOUT- (RL=1.2 kW) VFRO VFRO SGT, SGR SGT SGR Min. 10 20 1.2 1.2 -- -- -- -- -- -- -100 -20 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- 1.4 40 4 Max. -- -- -- -- 100 100 100 1.3 1.3 1.3 +100 +20 -- 80 8 Unit MW kW kW kW pF pF pF VPP VPP VPP mV mV V kW kW
*1 -7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0=1.30 VPP
15/38
Semiconductor Digital Interface Characteristics
MSM7718-01
(VDD= 2.7 to 3.6 V, Ta= -25 to +70C) Parameter Digital Output Delay Time PCM, ADPCM Interface Symbol tSDX, tSDR tXD1, tRD1 Condition Min. 0 0 0 0 50 20 20 50 100 50 50 0 50 50 0 EXCK 100 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 200 (100) 200 (100) 200 (100) 200 (100) -- -- -- -- -- -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
1LSTTL+100 pF pull-up resistance : 500 W Values in parentheses apply when tXD2, tRD2 Cload = 10 pF, tXD3, tRD3 pull-up resistance :2 kW
Serial Port Digital Input/Output Setting Time
tM1 tM2 tM3 tM4 tM5 tM6 tM7 tM8 tM9 tM10 tM11 tM12
Cload=100 pF
Shift Clock Frequency
fECK
PCM/ADPCM Output Timing
BCLKP SYNCP tXO PCMPCO PCMADO PCMLNO PCMACO tSDX 0 tXS 1 tSX tXD1 2 tWS tXD2 MSB 3 4 5 6 7 8 9 10
tXD3 LSB
Note : The timing for PCMADO, PCMLNO, and PCMACO shown above reperesents the timing when time slot 1 is selected.
BCLKA SYNCA tXO IS tSDX 0 tXS 1 tSX tXD1 2 3 4 5 6 7 8 9 10
tXD2 MSB LSB
tXD3
16/38
Semiconductor PCM/ADPCM Input Timing
BCLKA SYNCA IR 0 tRS 1 tSR tRO MSB 0 tRS SYNCP PCMPCI PCMADI PCMLNI PCMACI 1 tSR tRO MSB 2 3 2 tWS tDS tDH LSB 4 5 6 7 8 3 4 5 6 7 8
MSM7718-01
9
10
BCLKP
9
10
tDS tDH LSB
Note : The timing for PCMADI, PCMLNI, and PCMACI shown above represents the timing when time slot 1 is selected.
Serial Port Timing for Microcontroller Interface
DEN tM2 EXCK tM1 DIN 1 tM3 W/R tM4 A4 2 3 5 tM6 A1 6 tM7 A0 B7 tM8 DOUT B7 B1 B0 B1 tM5 7 13 14 tM9 B0 tM11 15 tM12 tM10
17/38
Semiconductor AC Characteristics
MSM7718-01
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Symbol LOSS T1 LOSS T2 LOSS T3 Transmit Frequency Response LOSS T4 LOSS T5 LOSS T6 LOSS R1 LOSS R2 Receive Frequency Response LOSS R3 LOSS R4 LOSS R5 SD T1 SD T2 Transmit Signal to Distortion SD T3 SD T4 SD T5 SD R1 SD R2 Receive Signal to Distortion SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking GT R2 GT R3 GT R4 GT R5 NIDLT Idle Channel Noise NIDLR Absolute Signal Amplitude Power Supply Noise Rejection Ratio AVT AVR PSRRT PSRRR -- 1020 Noise Freq.: 0 to 50 kHz (*3) 0 Noise Level: 50 mVpp (*2) GSX2 VFRO -- -- -- -- 1020 1020 1020 1020 Condition Freq.(Hz) level (dBm0) Others 0-60 300-3k 1020 3300 3400 3968.75 0-3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 AIN=SG (*2) -- -0.2 -0.5 -1.2 -- -- -0.2 -0.5 -1.2 -0.2 (*2) (*2) 0 -- -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 0 -- Min. 25 -0.15 -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- -- +0.2 +0.5 +1.2 -68 dBm0p (-75.7) (dBmp) -72 dBm0p (79.7) (dBmp) Vrms Vrms dB dB dB +0.2 +0.5 +1.2 +0.2 dB +0.8 0.8 -- -- -- -- -- -- -- -- -- -- -- +0.2 dB dB dB +0.8 0.8 -- +0.2 Max. -- +0.2 dB Unit
0.285 0.32(*4) 0.359 0.285 0.32(*4) 0.359 30 30 -- -- -- --
*2. P-message weighted filter used *3. PCMPCI input code: "11111111" (m-law) *4. 0.320 Vrms=0 dBm0=-7.7 dBm Note : All ADPCM coder and decoder characteristics fully comply with ITU-T Recommendations G.726. 18/38
Semiconductor AC Characteristics (DTMF and Other Tones)
MSM7718-01
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Frequence Deviation Symbol DfT1 DfT2 VTL Tone Reference Output Level (*5) Relative Value of DTMF Tones VTH VRL VRH RDTMF Transmit side tone Recieve side tone Condition DTMF Tones Other various tones DTMF (Low group) DTMF (Low group) (Gain set value:0dB) DTMF (High group), Others (Gain set value:0dB) DTMF (High group), Others VTH/VTL, VRH/VRL Min. Typ. Max. Unit -1.5 -1.5 -10 -8 -10 -8 1 -- -- -8 -6 -8 -6 2 +1.5 +1.5 % %
-6 dBm0 -4 dBm0 -6 dBm0 -4 dBm0 3 dB
*5 Not including programmable gain set values AC Characteristics (Gain Settings)
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Transmit/Recieve Gain Setting Accurancy Symbol DG Condition For all gain set values Min. Typ. Max. Unit -1 0 +1 dB
AC Characteristics (VOX Function)
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter Transmit VOX Detection Time voice signal ON/OFF Detect Time Transmit VOX Detection Level Accuracy (Voice Detection Level) Symbol tVXON tVXOFF DVX Condition SilenceAEvoice VoiceAEsilence CRM6-B6,B5
VOXO pin:see Fig.6 Voice/silence differential:10 dB
Min. --
Typ. 5
Max. --
Unit ms ms dB
140/300 160/320 180/340 -2.5 0 +2.5
For detection level set values by
19/38
Semiconductor AC Characteristics (Tone Detect Function)
MSM7718-01
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Parameter CPT Detection Frequency CPT Non-detection Frequency CPT Detection Level CPT Non-detection Level CPT Input Signal Continuation Time CPT Detection Delay Time CPT Detection Hold Time DTMF Detection Frequency DTMF Non-detection Frequency DTMF Detection Level DTMF Non-detection Level DTMF Input Signal continuation Time DTMF Detection Delay Time DTMF Detection Hold Time ANS Detection Frequency ANS Non-detection Frequency ANS Detection Level ANS Non-detection Level ANS Input Signal Continuation Time ANS Detection Delay Time ANS Detection Hold Time Symbol fdetcp frejcp Vdetcp Vrejcp tdetcp trejcp tdlycp tholcp fdetdt frejdt Vdetdt Vrejdt tdetdt trejdt tdlydt tholdt fdetan frejan Vdetan Vrejan tdetan trejan tdlyan tholan CPT detected CPT not detected -- -- CPT detected CPT not detected -- -- -- -- Input Frequency: 2079 to 2121 Hz -- CPT detected CPT not detected -- -- At Nominal Frequency At Nominal Frequency -- Condition -- -- Input Frequency: 350 to 640 Hz -- Min. Typ. Max. Unit 350 700 -- -39 -- 55 -- 30 7 -- 3.8 -- 38 -- 16 14 2350 -- -31 -- 480 -- 420 7 -- -- -- -- -- -- -- 45 16 -- -- -- -- -- -- -- -- -- -- -- -- -- 12 640 -- 250 0 -- 30 55 24 1.5 -- 0 -- 16 38 25 -- 0 -- 420 17 Hz Hz Hz dBm0 ms ms ms ms % % dBm0 ms ms ms ms Hz Hz Hz dBm0 ms ms ms ms
-49 dBm0
Input Frequency:Nominal Frequency 1.5% -39
-47 dBm0
2079 2100 2121 -- 1900
-35 dBm0
450 480
tdetXX INPUT SIGNAL
trejXX
DETECPT: CR7-B3 DETDTMF: CR7-B2 DET21L: CR7-B1 DET21L: CR7-B1 INT pin INT: CR7-B4 (positive logic)
tdlyXX
tholXX
The state of the INT pin is changed by reading the contents of CR7. It is retained when CR7 is not read.
Note : In the case of call progress tone, DTMF tone, and 2100 Hz tone, XX refers to cp, dt, and an respectively.
20/38
Semiconductor
MSM7718-01
FUNCTIONAL DESCRIPTION
Control Registers Table 1 Control Register Map
Address Reg Name A4 A3 A2 A1 A0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Contents B7 -- B6 PDWN B5 B4 -- B3 B2 B1 B0 PDN/ RST ADPCM ADPCM PCM AD MODE RESET SEL PCM PCO PCM PCI PCM LN MUTE MUTE SEL2 TX TX TX GAIN3 GAIN2 GAIN1 TX TONE TX TONE TX TONE GAIN3 GAIN2 GAIN1 DTMF/OTHERS TX TONE RX TONE SEL SEND SEND ON VOX ON LVL0 ON/OFF LVL1 VOX Silence level Silence level 1 0 OUT LECTHR LECCLR1 LECCLR2 (HCL)* AECTHR AECCLR -- (HCL)* SEND/ MEM ADPCM REC SEL MODE1 ST7/ ST6/ ST5/ A7 A6 A5 ST15/ ST14/ ST13/ A15 A14 A13 -- SP7 SP15 -- -- SP6 SP14 -- -- SP5 SP13 -- R/W
OPE OPE OPE OPE MODE3 MODE2 MODE1 MODE0 R/W TX RX RX RX RX MUTE MUTE MLV2 MLV1 MLV0 R/W PCM LN PCM LN PCM AC PCM AC PCM AC SEL1 SEL0 SEL2 SEL1 SEL0 R/W TX RX RX RX RX GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 R/W TX TONE RX TONE RX TONE RX TONE RX TONE GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 R/W TONE4 OFF TIME TONE3 TONE2 RX. NOISE LEVEL SEL DET DTMF LECHLD (ADP)* AECHLD (APD)* CMD2 ST2/ A2 ST10/ A10 ST18/ A18 SP2 SP10 SP18 TONE1 TONE0 R/W
VOX IN DET INT CPT LECHD LECCCLP (NLP)* AECCCLP AECHD (NLP)* ADPCM MODE0 CMD3 ST4/ ST3/ A4 A3 ST12/ ST11/ A12 A11 ST20/ ST19/ A20 A19 SP4 SP12 SP20 SP3 SP11 SP19
RX. NOISE RX. NOISE LVL1 LVL0 R/W BUSY/ RPM/ DET21L DET21A R LECATT LECGC R/W (ATT)* (GC)* AECATT AECGC R/W (ATT)* (GC)* CMD1 ST1/ A1 ST9/ A9 ST17/ A17 SP1 SP9 SP17 CMD0 R/W ST0/ A0 ST8/ A8 ST16/ A16 SP0 SP8 SP16 R/W R/W R/W R/W R/W R/W
D7/CA7 D6/CA6 D5/CA5 D4/CA4 D3/CA3 D2/CA2 D1/CA1 D0/CA0 R/W WA7 WA6 WA5 WA4 D TONE3/ D TONE2/ D TONE1/ WA3 WA2 WA1 D TONE0/ R/W WA0
R/W : Read/write enable R : Read only register * : These are the symbols of control pins used in the MSM7602 (echo canceler LSI device).
21/38
Semiconductor (1)CR0 (Basic operating mode settings)
B7 CR0 Initial value * -- 0 B6 PDWN 0 B5 PDN/RST 0 B4 -- 0 B3 OPE MODE3 0 B2 OPE MODE2 0
MSM7718-01
B1 OPE MODE1 0
B0 OPE MODE0 0
*:
Indicates the value to be set when a resetting is made through the PDN/RST pin. (Also when reset by bit 5 (B5, PDN/RST), the other bits of CR0 are reset to initial values.)
B7 ... Not used B6 ... Power-down (entire system) 0: Power-on 1: Power-down ORed with the inverted external power-down signals Set the PDWN pin to "1" when this data is used. The control registers and their internal variables are not reset. B5 ... Power-down reset (entire system) 0: Power-on 1: Power-down reset ORed with the inverted external power-down reset signals Set the PDN/RST pin to "1" when this data is used . B4 ... Not used B3, 2, 1, 0 ...... Selection of an operating mode (0, 0, 0, 0) : Initial mode This mode enables a change (see Figure 15-1, 2) in memory that contains internal default values such as tone generation frequencies. In this mode, the PCM output pin acts to output idle patterns and the PCM input pin acts to input idle patterns. When a reset or power-down occurs or when power down is released, the device enters the initial mode about 200 ms after that. (0, 0, 0, 1) : Reserved (0, 0, 1, 0) : Normal speech mode (see Figure 7-1) This mode enables call services between a slave telephone and a line (including tone generation) and detection of a DTMF tone and a call progress tone. The internal process enables the tone detector. The ADPCM encoder/decoder, the tone generator, and the line echo canceler become operative and can be controlled by the contents of the control registers. (0, 0, 1, 1) to (0, 1, 0, 0) : Reserved (0, 1, 0, 1) : Line echo canceler expansion mode (see Figure 7-2) This mode can expand the delay time of the line echo canceler up to 54 ms. Concerning the internal processing, the ADPCM encoder/decoder, the line echo canceler, and the tone generator become operative and can be controlled by the contents of the control registers. In addition, 2100 Hz tone of PCMLNI and PCMACI (bidirectional) can be detected. (0, 1, 1, 0) to (1, 1, 1, 1) : Reserved
22/38
Semiconductor
MSM7718-01
Tone Generator Tone Detector 23 ms Line Echo Canceler ADPCM CODER PCM CODEC ADPCM DECODER
Note : * When the MSM7718 is used in normal speech mode, set the TSTI4 pin to "0". * In normal speech mode, the tone detector can detect call progress tone and DTMF tone by PMLNI input.
MSM7718
Figure 7-1 Normal Speech Mode
Note : * When the MSM7718 is used in line echo Tone Detector canceler expansion mode, set the TSTI4 pin to digital "1". 54 ms Line * In line echo canceler expansion mode, the Echo Canceler tone detector can detect not only call progress tone and DTMF tone by PMLNI input but ADPCM CODER also 2100 Hz tone by PCMLNI and PCMACI PCM CODEC ADPCM DECODER input (bidirectional). * The PCM CODEC does not operate in this mode. A capacitor is required between SGT MSM7718 and ground and between SGR and ground Figure 7-2 Line Echo Canceler Expansion (see Application Circuit). Mode
Tone Generator
23/38
Semiconductor (2) CR1 (Setting of ADPCM operating mode and PCM I/O signals)
B7 CR1 Initial value ADPCM MODE 0 B6 ADPCM RESET 0 B5 PCM AD SEL 0 B4 TX MUTE 0 B3 RX MUTE 0 B2 RX MLV2 0
MSM7718-01
B1 RX MLV1 0
B0 RX MLV0 0
B7 ... ADPCM algorithm 0: 32 kbps (G.726) 1: Reserved B6 ... Transmitter/receiver ADPCM resetting (conforming to G.726) 1: Reset B5 ... PCM I/O multiple timing control (PCMADI and PCMADO pins) of the ADPCM CODEC 0: Time slot 1 1: Time slot 2 B4 ... Muting of transmitter ADPCM data 1: Mute B3 ... Muting of receiver ADPCM data 1: Muting specified by bits B2, B1, and B0 is enabled. This bit is valid when the MUTE pin is "0". B2, B1, B0 ... Setting of a receiver voice path mute level (MLV2, MLV1, MLV0) = (0, 0, 0) : (0, 0, 1) : (0, 1, 0) : (0, 1, 1) : (1, 0, 0) : (1, 0, 1) : (1, 1, 0) : (1, 1, 1) : Through - 6 dB -12 dB -18 dB -24 dB -30 dB -36 dB MUTE
24/38
Semiconductor (3) CR2 (Setting of PCM I/O multiple control)
B7 CR2 Initial value PCM PCO MUTE 0 B6 PCM PCI MUTE 0 B5 PCM LN SEL2 0 B4 PCM LN SEL1 0 B3 PCM LN SEL0 0 B2 PCM AC SEL2 0
MSM7718-01
B1 PCM AC SEL1 0
B0 PCM AC SEL0 0
B7 ... ON or OFF of the PCM signal of the transmitter side of the PCM CODEC (PCMPCO pin) 0: ON 1: OFF When this bit is "1" (OFF), the PCMPCO pin transmits a PCM idle pattern. B6 ... ON or OFF of the PCM signal of the receiver side of the PCM CODEC (PCMPCI pin) 0: ON 1: OFF When this bit is "1" (OFF), the PCMPCI pin receives a PCM idle pattern. B5, 4, 3 .... PCM I/O multiple timing control (PCMLNI and PCMLNO pins) of the line echo canceler (see Table 2) B2, 1, 0 .... PCM I/O multiple timing control (PCMACI and PCMACO pins) of the line echo canceler (see Table 2)
Table 2 PCM Multiple Timing Control Table
B5 ( B2 0 0 0 0 1 1 1 1 B4 B1 0 0 1 1 0 0 1 1 B3 B0 ) 0 1 0 1 0 1 0 1 Corresponding time slot None 1 2 3 4 5 6 7
Note : When bits B5 to B3 or B2 to B0 are all zeros, the internal process inputs a PCM idle pattern. In this case, the outputs are all in high impedance state for all time slots.
25/38
Semiconductor (4) CR3 (Transmit/receive gain adjustment)
B7 CR3 Initial value TX GAIN3 0 B6 TX GAIN2 0 B5 TX GAIN1 0 B4 TX GAIN0 0 B3 RX GAIN3 0 B2 RX GAIN2 0
MSM7718-01
B1 RX GAIN1 0
B0 RX GAIN0 0
B7, 6, 5, 4 ...... Adjustment of the transmit signal gain [ATTtx] (see Table 3) B3, 2, 1, 0 ...... Adjustment of the receive signal gain [ATTrx] (see Table 3) Table 3 Transmit/Receive Signal Gain Setting
B7 1 1 1 1 1 1 1 1 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit signal gain -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive signal gain -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 dB +2 dB +4 dB +6 dB +8 dB +10 dB +12 dB +14 dB
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 dB +2 dB +4 dB +6 dB +8 dB +10 dB +12 dB +14 dB
This table is for gains of transmit/receive voice signals.
26/38
Semiconductor (5) CR4 (Adjustment of tone generator gain)
B7 CR4 Initial value TX TONE GAIN3 0 B6 TX TONE GAIN2 0 B5 TX TONE GAIN1 0 B4 TX TONE GAIN0 0 B3 RX TONE GAIN3 0 B2 RX TONE GAIN2 0
MSM7718-01
B1 RX TONE GAIN1 0
B0 RX TONE GAIN0 0
B7, 6, 5, 4 ...... Transmit side gain adjustment for the tone generator [ATTtgtx] (see Table 4) B3, 2, 1, 0 ...... Receive side gain adjustment for the tone generator [ATTtgrx] (see Table 5) Table 4 Setting of Transmit Side Gain of Tone Generator
B7 0 0 0 0 0 0 0 0 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Tone generator gain -36 dB -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B7 1 1 1 1 1 1 1 1 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Tone generator gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB
Table 5 Setting of Receive Side Gain of Tone Generator
B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone generator gain -36 dB -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone generator gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB
Settings of Table 5 are made in relation to the following tone levels: DTMF tone (Low frequency group) : -2 dBm0 DTMF tone (High frequency group) and other tone : 0 dBm0 For example, when bits B3, B2, B1, and B0 are set to "1, 1, 1, 1" (-6 dB), the PCMLNO pin outputs a tone of the following levels: DTMF tone (Low frequency group) : -8 dBm0 DTMF tone (High frequency group) and other tone : -6 dBm0 The default value change command enables the gain adjustment by -1 dB step. Writing "13CAh" into the address 00D8h adds a gain of -1 dB to the values in the above table. The default value is "1634h".
27/38
Semiconductor (6) CR5 (Setting of tone generator operating mode and tone frequency)
B7 CR5 Initial value SEL 0 B6 SEND 0 B5 RX TONE SEND 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0
MSM7718-01
B1 TONE1 0
B0 TONE0 0
DTMF/OTHERS TX TONE
B7 ... Selection of DTMF signal or others (S, F, or R tone) 0: Others 1: DTMF signal B6 ... Transmission of transmit side tone 0: Not transmit 1: Transmit B5 ... Transmission of receive side tone 0: Not transmit 1: Transmit B4, 3, 2, 1, 0 ... Setting of a tone frequency (see Table 6) Table 6 Setting of Tone Generator Frequencies (a) when B7 = "1" (DTMF tone)
B4 B3 B2 B1 B0 * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description 697 Hz + 1209 Hz (1) 697 Hz + 1336 Hz (2) 697 Hz + 1477 Hz (3) 697 Hz + 1633 Hz (A) 770 Hz + 1209 Hz (4) 770 Hz + 1336 Hz (5) 770 Hz + 1477 Hz (6) 770 Hz + 1633 Hz (B) B4 B3 B2 B1 B0 * * * * * * * * 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description 852 Hz + 1209 Hz (7) 852 Hz + 1336 Hz (8) 852 Hz + 1477 Hz (9) 852 Hz + 1633 Hz (C) 941 Hz + 1209 Hz (*) 941 Hz + 1336 Hz (0) 941 Hz + 1477 Hz (#) 941 Hz + 1633 Hz (D)
(b) When B7 = "0" (Others) The Table below lists default frequencies. "00000" to "00011" ("B4, B3, B2, B1, B0") are tones, which are modulated by sinewave. "01000" to "01011" are wamble tones, and "10000" to "10111" are single tones. For procedures to change frequencies, see the next page.
B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description
400/0H - 16 Hz Sine wave modulation 3000/0H - 16 Hz Sine wave modulation 2700/0H - 16 Hz Sine wave modulation */*H - 16 Hz Sine wave modulation
B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
Description 400 Hz Single tone 1000 Hz Single tone 2000 Hz Single tone 2667 Hz Single tone 1300 Hz Single tone 2080 Hz Single tone *Hz Single tone *Hz Single tone -- -- -- -- -- -- -- --
-- -- -- -- 513/636 Hz 12 Hz Wamble 800/1000 Hz 8 Hz Wamble 2000/2667 Hz 8 Hz Wamble */*Hz *Hz Wamble -- -- -- --
28/38
Semiconductor
MSM7718-01
Frequencies of tones (other than DTMF signals) to be generated by the tone generator can be changed. Tone frequencies can be changed in the Initial mode. See Figure 15-1 for procedures to change tone frequencies. The related subaddresses are shown below.
Modulation by 16 Hz sine wave
B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Subaddress 1 (Frequency 1) *1 164h 165h 166h 167h 62.5 ms Modulation by 16 Hz sine wave
Wamble
B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 Subaddress 1 (Frequency 1) *1 168h 169h 16Ah 16Bh Subaddress 2 (Frequency 2) *1 16Ch 16Dh 16Eh 16Fh Subaddress 3 (Time 1) *2 170h 171h 172h 173h Subaddress 4 (Time 2) *2 174h 175h 176h 177h
Single tone
B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Subaddress 1 (Frequency 1) *1 178h 179h 17Ah 17Bh 17Ch 17Dh 17Eh 17Fh Time 1 62.5 ms Time 2 62.5 ms 8 Hz wamble tone
Transmit single tone
*1 Transmitted Tone Frequency = A 8.192 (A = frequency) ex. When frequency = 1000 Hz, 1000 8.192 = 9011.2 = 9011d (eliminate after the decimal point) = 2333h Wamble Frequency (Tone Transmit time) = (A/B)/2 - 1 (A = Transmitted tone frequency, B = wamble frequency) ex. When wamble frequency is 8 Hz, tone frequency = 2667 Hz. (2667/8)/2 - 1 = 166.69 = 166d (eliminate after the decimal point) = A6h *2
29/38
Semiconductor (7)CR6 (VOX function control)
B7 CR6 Initial value VOX ON/OFF 0 B6 ON LVL1 0 B5 ON LVL0 0 B4 OFF TIME 0 B3 VOX IN 0 B2 RX. NOISE LEVEL SEL 0
MSM7718-01
B1 RX. NOISE LVL1 0
B0 RX. NOISE LVL0 0
B7 ... Turns ON or OFF the VOX function. 0: OFF, 1: ON B6, 5 ... Setting of transmit side voice or silence detection level (0, 0) : -20 dBm0 (0, 1) : -25 dBm0 (1, 0) : -30 dBm0 (1, 1) : -35 dBm0 Note: * The detection level is changeable by inserting the pad of -1 dB to -5 dB in addition to the above values. * Write 16384 10 (-A/20) at address "175h". (A=pad) Example: When -1 dB pad is inserted, 16384 10 (- (-1)/20) =18383.15=18383d (eliminate after the decimal point)=47CFh B4 ... Setting of hangover time (TVXOFF) (see Figure 6) 0: 160 ms 1: 320 ms B3 ... VOX input signal (receiver side) 0: Transmits an internal background noise. 1: Transmits a voice reception signal. Set the VOXI pin to "0" to use this data. B2 ... Setting of a receiver side background noise level 0: Automatic internal setting 1: Reserved B1, 0 ... Externally-set background noise level (0, 0) : No noise (0, 1) : -55 dBm0 (1, 0) : -45 dBm0 (1, 1) : -35 dBm0 (8) CR7 (Detection register : read-only)
B7 CR7 Initial value VOX OUT 0 B6 1 0 B5 0 0 B4 INT 0 B3 DET CPT 0 Silence level Silence level B2 DET DTMF 0 B1 BUSY/ DET21L 0 B0 PRM/ DET21A 0
B7 ... Detection of transmit side voice or noise 0: Silence 1: Voice B6, 5 ... Transmit side silence level (indicator) (0, 0) : -10 dB or less with respect to the detection level defined by CR6-B6, B5. (0, 1) : -5 to -10 dB with respect to the detection level defined by CR6-B6, B5. (1, 0) : 0 to -5 dB with respect to the detection level defined by CR6-B6, B5. (1, 1) : 0 dB or more. Refer to the detection level defined by CR6-B6, B5. Note : The above outputs are valid only when the VOX function is enabled by bit 7 of CR6. B4 ... External interrupt signal Goes to a logic "0" when any change has been found in the tone detection results for call progress tone, DTMF tone, and 2100 Hz tone. Goes to a logic "1" when the CR7 control register is read out . The inverted state of this bit (B4) is output to the INT pin. 30/38
Semiconductor B3 ... Detection of a call progress tone 1: Detected B2 ... Detection of a DTMF tone 1: Detected B1 ... PCMLNI input 2100 Hz tone detection (DET21L: expansion mode) 1: Detected 0: Not detected B0 ... PCMACI input 2100 Hz tone detection (DET21A: expansion mode) 1: Detected 0: Not detected (9) CR8 (Setting of line echo canceler operating mode)
B7 CR8 Initial value LECTHR (HCL)*1 1 B6 B5 B4 LECHD 0 B3 LECCCLP (NLP)*1 0 B2 LECHLD (ADP)*1 0
MSM7718-01
0: Not detected 0: Not detected valid only in the line echo canceler
valid only in the line echo canceler
B1 LECATT (ATT)*1 0
B0 LECGC (GC)*1 0
LECCLR1 LECCLR2 0 0
*1 Names of control pins used in the MSM7602 B7 ... "Through" mode control bit for the line echo canceler. In the "Through" mode, RinL and SinL data is output directly to RoutL and SoutL respectively. 1: "Through" mode 0: Normal mode (echo cancellation) B6 ... Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (LAFF) used by the line echo canceler. 1: Resets the coefficient 0: Normal operation B5 ... Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (LAFF) used by the line echo canceler. 1: Resets the coefficient 0: Normal operation B4 ... Howling detector (HD) ON/OFF control 1: ON 0: OFF B3 ... Turns ON or OFF the center clip function which forcibly sets the SoutL output of the line echo canceler to minimum positive value when it is -57 dBm0 or less. 1: Center clip function ON 0: Center clip function OFF B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (LAFF) for the line echo canceler. 1: Coefficient fixed mode 0: Normal mode (updates the coefficient) B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of attenuators ATTsL and ATTrL provided for the RinL input and the SoutL output of the line echo canceler. When a signal is input to RinL only, the attenuator ATTsL of the SoutL output is activated. When a signal is input to SinL only or to both SinL and RinL, the attenuator ATTrL of the RinL input is activated. Their ATT values are both about 6 dB. 1: ATT OFF 0: ATT ON B0 ... Turns ON or OFF the gain control function which controls the RinL input level and prevents howling from occurring by the gain controller (GainL) for the RinL input of the line echo canceler. The gain controller adjusts the RIN level when it is -24 dBm0 or above, and it has the control range of 0 to -8.5 dB. 1: Gain control ON 0: Gain control OFF 31/38
Semiconductor
MSM7718-01
(10) CR9 : Reserved (Setting of acoustic echo canceler operating mode)
B7 CR9 Initial value AECTHR (HCL)*1 1 B6 -- 0 B5 AECCLR 0 B4 AECHD 0 B3 AECCCLP (NLP)*1 0 B2 AECHLD (ADP)*1 0 B1 AECATT (ATT)*1 0 B0 AECGC (GC)*1 0
*1 Names of control pins used in the MSM7602 B7 ... Acoustic echo canceler through-mode control bit In this mode, RinA data and SinA data are through-output to RoutL and SoutL respectively. 1: Through mode 0: Normal mode (echo cancellation) B6 ... Not used B5 ... Selects whether or not to clear the coefficient of the adaptive FIR filter (AAFF) for the acoustic echo canceler. 1: Resets the coefficient 0: Normal operation B4 ... Howling detector (HD) ON/OFF control 1: ON 0: OFF B3 ... Turns ON or OFF the center clip function which forcibly sets the Sout output of the acoustic echo canceler to a minimum positive value when it is -57 dBm0 or less. 1: Center clip function ON 2: Center clip function OFF B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (AAFF) for the acoustic echo canceler. 1: Coefficient Fixed mode 0: Normal mode (updates the coefficient.) B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of attenuators ATTrA and ATTsA provided for the RinA input and the SoutA output of the acoustic echo canceler. When a signal is input to RinA only, the attenuator ATTsA of the SoutA output is activated. When a signal is input to SinA only or to both SinA and RinA, the attenuator ATTrA of the RinA input is activated. Their ATT values are both about 6 dB. 1: ATT OFF 0: ATT ON B0 ... Turns ON or OFF the gain control function which controls the RinA input level and prevents howling from occurring by the gain controller (GainA) for the RinA input of the acoustic echo canceler. The gain controller starts controlling when the RIN level is -24 dBm0 or above and has the control range of 0 to -8.5 dB. 1: Gain control ON 0: Gain control OFF
32/38
Semiconductor (11) CR10 (External memory (flash memory) interface control)
B7 CR10 Initial value SEND/ REC 0 B6 MEM SEL 0 B5 ADPCM MODE1 0 B4 ADPCM MODE0 0 B3 CMD3 0 B2 CMD2 0
MSM7718-01
B1 CMD1 0
B0 CMD0 0
B7 ... Reserved (connection to the recording interface) B6 ... Reserved (selection of external memory) B5, 4 ... Reserved (selection of recording/playback ADPCM compression mode) B3, 2, 1, 0 ... Reserved (memory interface command) (0, 0, 0, 0) : NOP (0, 0, 0, 1) : Reserved (0, 0, 1, 0) : Reserved (0, 0, 1, 1) : Reserved (0, 1, 0, 0) : Reserved (0, 1, 0, 1) : Reserved (0, 1, 1, 0) : Reserved (0, 1, 1, 1) : Reserved (1, 0, 0, 0) : Reserved (1, 0, 0, 1) : Reserved (1, 0, 1, 0) : Reserved (1, 0, 1, 1) : Reserved (1, 1, 0, 0) : Reserved (1, 1, 0, 1) : MDWR (Change default) Writes the data of CR17 (D0 to D7) and CR16 (D8 to D15) in the lower byte of default storage memory. The address is specified by A0 to A7 of CR11 and A8 to A15 of CR12. (1, 1, 1, 0) : Reserved (1, 1, 1, 1) : Reserved
33/38
Semiconductor
MSM7718-01
(12) CR11, 12, 13 (Memory address register 1)
B7 CR11 Initial value ST7/ A7 -- B7 CR12 Initial value ST15/ A15 -- B7 CR13 Initial value -- -- B6 ST6/ A6 -- B6 ST14/ A14 -- B6 -- -- B5 ST5/ A5 -- B5 ST13/ A13 -- B5 -- -- B4 ST4/ A4 -- B4 ST12/ A12 -- B4 ST20/ A20 -- B3 ST3/ A3 -- B3 ST11/ A11 -- B3 ST19/ A19 -- B2 ST2/ A2 -- B2 ST10/ A10 -- B2 ST18/ A18 -- B1 ST1/ A1 -- B1 ST9/ A9 -- B1 ST17/ A17 -- B0 ST0/ A0 -- B0 ST8/ A8 -- B0 ST16/ A16 --
CR11 to 13 : Registers storing an address (A0 to A20) required for the default value change command Since CR13 is assigned "0h", no setting is requited for it. (13) CR14, 15, 16 (Memory address register 2)
B7 CR14 Initial value SP7 -- B7 CR15 Initial value SP15 -- B7 CR16 Initial value -- -- B6 SP6 -- B6 SP14 -- B6 -- -- B5 SP5 -- B5 SP13 -- B5 -- -- B4 SP4 -- B4 SP12 -- B4 SP20 -- B3 SP3 -- B3 SP11 -- B3 SP19 -- B2 SP2 -- B2 SP10 -- B2 SP18 -- B1 SP1 -- B1 SP9 -- B1 SP17 -- B0 SP0 -- B0 SP8 -- B0 SP16 --
CR14 to 16:
When the default value change command is used, the bit 7 to bit 0 of CR16 correspond to the D15 to D8 of write data.
Note : CR14 and CR15 are the reserved registers.
34/38
Semiconductor (14) CR17 (Memory data register)
B7 CR17 Initial value D7/CA7 -- B6 D6/CA6 -- B5 D5/CA5 -- B4 D4/CA4 -- B3 D3/CA3 -- B2 D2/CA2 --
MSM7718-01
B1 D1/CA1 --
B0 D0/CA0 --
CR17 is the register to store the data used by the default value store command. (15) CR18 (Setting of tone detection frequency, memory address register 3)
B7 CR18 Initial value WA7 -- B6 WA6 -- B5 WA5 -- B4 WA4 0 B3 WA3 0 B2 WA2 0 B1 WA1 0 B0 WA0 0
D TONE3/ D TONE2/ D TONE1/ D TONE0/
D TONE3 to 0: Valid only when the tone generator is operating (except for the initial mode) B7, 6, 5, 4 ... Not used B3, 2, 1, 0 ... Setting of a tone frequency (see Table 7) Table 7 Setting of Tone Detector Frequencies
B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 697 Hz + 1209 Hz (1) 770 Hz + 1209 Hz (4) 852 Hz + 1209 Hz (7) 941 Hz + 1209 Hz (*) 697 Hz + 1336 Hz (2) 770 Hz + 1336 Hz (5) 852 Hz +1336 Hz (8) 941 Hz + 1336 Hz (0) B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 697 Hz + 1477 Hz (3) 770 Hz + 1477 Hz (6) 852 Hz + 1477 Hz (9) 941 Hz + 1477 Hz (#) 697 Hz + 1633 Hz (A) 770 Hz + 1633 Hz (B) 852 Hz + 1633 Hz (C) 941 Hz + 1633 Hz (D)
35/38
Semiconductor Direct Access to Default Store Memory (See Figs.8-1, 8-2) The contents of the default store memory can be changed (e.g., to change tone detection levels and tone generation frequencies) in the initial mode (CR0-B3 to CR0-B0="0000"). Refer to the following procedure: 1.Set the default value store memory address (CR11, CR12). Set the write data into CR16 and CR17. 2.When writing data to the upper byte, set the DMWR (change default) command (CR10-B3 to CR10-B0="1101").
MSM7718-01
Default Value Store Memory Direct Access Set address. Set write data. Set command to write in upper byte (DMWR)
(1) CR12, CR11 CR16, CR17
(2) CR10
Yes
Continue to write? No END
Figure 8-1 Flow Chart of Default Value Store Memory Direct Access
Default Value Store Memory
Data (CR16, CR17)
Address (CR11, CR12)
Figure 8-2 Memory Map for Default Value Store Memory Direct Access
36/38
Semiconductor
MSM7718-01
APPLICATION CIRCUIT
MSM7718 IS IR VDDD1,2,3 VDDA SGT SGR AG DG1,2,3 AIN1+ AIN1- GSX1 AIN2 GSX2 VFRO PWI AOUT- AOUT+ A20-19 A18-0 D7-0 WE OE MCK PDN/RST PDWN EXCK DEN DIN DOUT INT RP BCLKA SYNCA VOXO VOXI PCMPCI PCMPCO PCMLNI PCMLNO PCMACI PCMACO PCMADI PCMADO BLKP SYNCP ADPCM Transmit Data ADPCM Receive Data ADPCM Control
1 mF
+ -
10 mF 1 mF
+ 10 mF -
1 mF
Voice Analog Input (Vi)
1 mF R1 R2 R4 R5
Transmit Gain (VGSX2/Vi) = (R2/R1) (R4/R3) Receive Gain (VO/VVFRO) = 2 R5/R6 Receiver Output VO
1 mF R3 R6
ZL = 120 nF + 350 W
PCM Control
Basic Controller
CS1 CS2
37/38
Semiconductor
MSM7718-01
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
38/38

▲Up To Search▲

Price & Availability of MSM7718-01

	To Download MSM7718-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .